Parallel implementations are often used in high-current applications and high-frequency applications. To achieve high drive currents, metal-oxide-semiconductor (MOS) transistors are connected in parallel to form a single transistor, with the gates interconnected with each other, sources interconnected with each other, and drains interconnected with each other.
FIGS. 1 through 3 illustrate several commonly used parallel implementations, wherein gate electrodes of MOS transistors are parallel to each other. In each of FIGS. 1 through 3, letters “G” represent gates, letters “S” represent sources, and letters “D” represent drains. FIG. 1 illustrates an implementation with the active regions (including respective sources S and drains D) of the individual MOS transistors physically separated from each other. FIG. 2 illustrates an implementation wherein each of sources S and drains D may be shared by two neighboring MOS transistors, and the MOS transistors are aligned to a single direction. FIG. 3 illustrates an implementation wherein each of sources S and drains D may be shared by two neighboring MOS transistors, and the MOS transistors are arranged into an array. It was observed that these implementations suffer from various drawbacks. For example, the implementation shown in FIG. 1 suffers from poly (gate electrode) loading effect, and the critical dimensions of the poly gates are difficult to control. The poly gate electrodes may be wider at the middle and narrower at ends. Further, the IR drop in implementations shown in FIGS. 1 and 2 may be high due to long metal lines required to interconnect gates, sources, and drains. The implementations shown in FIGS. 2 and 3 may further suffer from length of diffusion (LOD) problems.
In addition to the above-described drawbacks, due to the asymmetric layouts, it is difficult to construct models for the implementations shown in FIGS. 1 through 3. The reason is that the behavior of these MOS transistors not only changes with the number of individual MOS devices connected in parallel, but also changes with the gate widths.